A low-resistivity gate electrode is required to reduce speed limitations of MOS devices due to the gate RC delay time, especially in sub-quarter-micron ultra-large scale integrated circuits (ULSIs). Tungsten (W)-poly-silicon (poly) gate structures are known to have lower sheet resistance than conventional poly or policide gates. Because W reacts with poly at temperature as low as 600.degree. C., it is critical to have a high quality diffusion barrier between the two materials. Tungsten nitride (WN) and Titanium Nitride (TiN) are known diffusion barriers between W and poly to avoid silicidation of the W film.
In conventional post-gate-etch dry/wet oxidation to remove the etch damage and to improve the gate dielectric strength, all metal material, including the barrier, is subjected to oxidation. However, under selective oxidation conditions, such as wet hydrogen oxidation (WHO), only Si is oxidized, while tungsten-based materials are not oxidized in post-gate-etch oxidation. The method is based on the thermodynamic control of the equilibrium: EQU Si+2H.sub.2 O.revreaction.SiO.sub.2 +2H.sub.2 EQU W+3H.sub.2 O.revreaction.WO.sub.3 +3H.sub.2
With proper control of H.sub.2 O and H.sub.2 partial pressure, the equilibrium for the first reaction is favored towards the right, while the second equilibrium prefers to go to the left. Therefore, under appropriate conditions it is possible to oxidize silicon (Si) while the oxidation rate of W is very small. On the other hand, the oxidation of TiN is much more favorable than the reduction of TiO.sub.2, which makes the selective oxidation of W/TiN/Si system non-feasible. Therefore, considering the importance of low-resistivity and from a process integration point of view, a W-poly gate electrode without TiN is preferred.
Existing processes to fabricate W/WN/poly stack gate electrodes are based on a physical vapor deposition (PVD) process. For instance, WN.sub.x films are deposited on poly by reactive sputtering a W target in a gas mixture consisting of Ar:N.sub.2 =1:1. W films are then continuously deposited using a DC magnetron. However, the application of the above process to MOS devices with severe topography is limited due to the poor step coverage of PVD films. In addition, excess nitrogen in the WN.sub.x layer poses a potential problem for causing delamination as the gas may escape from the stack during subsequent thermal treatment. The typical process for depositing a diffusion barrier has a relatively low effective throughput, sometimes less than 20 wafers per hour.
There remains a need in the art for low-resistance W-poly gate structures and an effective and efficient process for forming barriers used in the W-poly gate structures.